Cisco has expanded its Cisco Silicon One portfolio by introducing two new 5 nm devices designed for web-scale spine roles and Ethernet-based artificial intelligence/machine learning (AI/ML) deployments.
The chips are being tested by five of the six major cloud providers, Cisco said, without naming the firms. Key cloud players include Amazon Web Services, Microsoft Azure and Google Cloud, which together dominate the market for cloud computing, according to Bofa Global Research.
In April, Broadcom announced the Jericho3-AI chip that can connect up to 32,000 GPU chips together.
This expansion enhances the Cisco Silicon One lineup, which covers a wide range from 3.2 Tbps to 51.2 Tbps, offering a unified architecture and software development kit that ensures seamless convergence without any compromises, Cisco’s Rakesh Chopra said in a blog post.
The introduction of the Cisco Silicon One G200 and G202, which Cisco is sampling to customers, brings exceptional advancements to the industry, providing advanced features that optimize the real-world performance of AI/ML workloads.
Additionally, these devices significantly reduce network costs, power consumption, and latency through groundbreaking innovations. Remarkably, these chips represent the fourth generation of devices in the Cisco Silicon One portfolio, which was initially launched a mere three and a half years ago.
Cisco Silicon One G200 is a 5 nm, 51.2 Tbps device equipped with a 512 x 112 Gbps serializer-deserializer (SerDes). This uniquely programmable, deterministic, and low-latency device offers advanced visibility and control, making it the ideal choice for web-scale networks.
Cisco Silicon One G202 is suitable for customers seeking to leverage 50G SerDes for optic connections to the switch. The G202 is a 5 nm, 25.6 Tbps device equipped with a 512 x 56 Gbps SerDes, offering half the performance while still delivering impressive capabilities.
Seven years ago, Cisco initiated its investment in high-speed SerDes development, recognizing the need to transition to analog-to-digital (ADC)-based SerDes as speeds increased. SerDes plays a critical role as a fundamental networking interconnect component for high-performance computing and AI deployments.
Cisco Silicon One G200 showcases the industry’s first fully custom, P4 programmable parallel packet processor capable of launching over 435 billion lookups per second. It offers advanced features such as SRv6 Micro-SID (uSID) at full rate and supports full run-to-completion processing for complex flows. This unique packet processing architecture ensures flexibility with deterministic low latency and power consumption.
Cisco Silicon One G200 sets itself apart with a higher radix compared to alternative solutions, boasting 512 Ethernet MACs. This allows customers to significantly reduce the cost, power consumption, and latency of their network deployments by eliminating unnecessary layers.
Notably, Silicon One G200 is capable of driving 43 dB bump-to-bump channels, enabling the utilization of co-packaged optics (CPO), linear pluggable objects (LPO), and the use of 4-meter 26 AWG copper cables, surpassing IEEE standards for optimal in-rack connectivity.
When compared to Cisco Silicon One G100 device, the Silicon One G200 demonstrates over two times greater power efficiency and two times lower latency, further solidifying its position as a remarkable advancement in networking technology.
